A functional test in a semiconductor integrated circuit is typically performed by the following procedure. First, a test input signal is inputted to a semiconductor integrated circuit to be tested and a test output signal outputted in response to the input is received by an LSI testing apparatus. The LSI testing apparatus compares the test output signal outputted from the semiconductor integrated circuit with a test expected value signal indicating an output state during a normal operation and judges the result of the comparison, thereby testing whether or not the semiconductor integrated circuit is normally operating.
To perform a functional test as described above, it is necessary to provide dedicated test terminals capable of directly inputting the test input signal to a circuit under test and directly outputting the test output signal or shared test terminals used also as the external terminals of an LSI (hereinafter referred to as the dedicated/shared test terminals).
However, as semiconductor integrated circuits become larger in scale and more complicated, the number of the dedicated/shared test terminals required to input and output test signals tends to increase. As a conventional method for suppressing such an increase in the number of test terminals, a test method termed BIST (Built in Self Test) has been known (see Patent Document 1). The BIST is a test method which causes the test input signal and the test expected value signal each required to perform the functional test in the LSI testing apparatus to be generated within the circuit under test, causes expected value judging means provided within the circuit to make a comparison and judge the result of the comparison, and causes only the result of the judgment to be outputted from the semiconductor integrated circuit.
This eliminates the need to directly input the test signal to the circuit under test from outside the LSI and directly output the test signal from the circuit under test. As a result, it is possible to suppress the increase in the number of the test terminals by providing only a minimum number of terminals required to implement the BIST as the test terminals.
Patent Document: Japanese Laid-Open Patent Publication No. 2004-93421